FTM2=0, DMAMUX=0, CRC=0, SPI1=0, FTM1=0, FTM0=0, ADC0=0, PDB0=0, FLEXCAN0=0, FTF=0, FTM3=0, PIT=0, DAC0=0, FLEXCAN1=0, SPI0=0, PDB1=0
System Clock Gating Control Register 6
FTF | Flash Memory Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DMAMUX | DMA Mux Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FLEXCAN0 | FlexCAN0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FLEXCAN1 | FlexCAN1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM3 | FTM3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
SPI0 | SPI0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
SPI1 | SPI1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PDB1 | PDB1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
CRC | CRC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PDB0 | PDB0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PIT | PIT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM0 | FTM0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM1 | FTM1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
FTM2 | FTM2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
ADC0 | ADC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
DAC0 | DAC0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |